Merced, EPIC, & IA64 Explained

A big problem with processors nowadays is memory latencies. Increasing cache sizes can only go so far, and CPU developers must constantly worry about whether or not RAM designers is going to come up with faster RAM, and also about how to deal with increasing latencies. (RAM "runs" much slower than a processor) EPIC architecture has an good solution for dealing with the latency problem. EPIC processors are capable of scheduling a load instruction even BEFORE a branch is entered. This process is called speculation. The problem here is, what happens if there is an invalid value, (e.x. a value not yet defined). Normally, this would generate an exception, and the program would crash. In EPIC systems; however, the processor remembers that it did a speculative load which may not be defined and continues processing. When it needs the data, the processor checks back to verify the data. If the data is valid, then the CPU can use it, saving a lot of time. (Since the processor had a while to do the load, since it was initiated before the branch)

Speculation and Predication in Action

Taken from Next Generation Instruction Site Architecture (from Intel & HP), Intel and HP use a portion of the 8 Queens problem (position 8 queens on a chess board so that none of them are attacking each other.) to demonstrate the power of Speculation and Predication. To view the entire slide show of this portion. (Quite informative) Click here.